7400 Series Clock

Some time around 2018 I read that the 60 Hz mains frequency used across North America is actually very stable. While the frequency was rather slow, an obvious application, I thought, was as a time-base in a clock. After some research I realized this was hardly a new idea. This was a simple project that I was able to design and think through as I went, without much planning before hand (I think deciding on an enclosure was the most time consuming step). Regarding the actual period of the time-base: I find that the clock was much more accurate in Seneca than in Summerville. It deviated by ~2 minutes over 4 months in my apartment, but it’s drifted about 7 minutes in the two weeks that it’s been running here.

The division logic is straightforward but I’ve opted to include the combinational circuit that drives the “12”, which is a bit more complex (this part certainly wasn’t done in my head).

Note that the driver seen above makes use of NAND gates combinations that form Boolean equivalents of other gates. Why? I came up empty-handed on the ones I needed and had to dip into my reserve supply, which was mostly NANDs. It’s also worth noting that the bus toward the top is the input from the previous (i.e. minutes) counter stage. The bus toward the bottom of the diagram has four bit-masked lines which drive a standard BCD-7 Seg decoder, and an extra, fifth line that drives the left digit directly. The D flip-flop greatly simplified the circuitry involved in driving the “12”, and the fact that it’s edge-triggered instead of level-triggered like its neighbors has never been a problem. Of course the left digit either displays a “1” or nothing, so only one bit was needed to control it.

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